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NTE7133 Integrated Circuit Horizontal and Vertical Deflection Controller for VGA/XGA and Autosync Monitors
Description: The NTE7133 is an integrated circuit in a 20-Lead DIP type package. This device is designed to provide an economical solution in VGA/XGA and autosync monitors by incorporating complete horizontal and vertical small signal processing. VGA-dependent mode detection and setting are performed on-chip. Features: D VGA Operation Fully Implemented Including Alignment-Free Vertical and E/W Amplitude Pre-Settings D 4th VGA Mode Easy Applicable (XGA, Super VGA) D Autosync Operation Externally Selectable D Low Jitter D All Adjustments DC-Controllable D Alignment-Free Oscillators D Sync Separators for Video or Horizontal and Vertical TTL Sync Levels Regardless or Polarity D Horizontal Oscillator with PLL1 for Sync and PLL2 for Flyback D Constant Vertical and E/W Amplitude in Multi-Frequency Operation D DC-Coupling to Vertical Power Amplifier D Internal Supply Voltage Stabilization with Excellent Ripple Rejection to Ensure Stable Geometrical Adjustments Absolute Maximum Ratings: Supply Voltage (Pin1), VP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +16V Voltage (Pin3, Pin7), V3, V7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +16V Voltage (Pin8), V8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +7V Voltage (Pin5, Pin6, Pin9, Pin10, Pin13, Pin14, Pin18), Vn . . . . . . . . . . . . . . . . . . . . . . -0.5 to +6.5V Current (Pin2), I2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA Current (Pin3), I3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA Current (Pin7), I7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Current (Pin8), I8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10mA Electrostatic Handling for All Pins (Note 1), Vesd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400V Operating Junction Temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150C Operating Ambient Temperatrure Range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +70C Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to +150C Thermal Resistance, Junction-to-Ambient (In Free Air), RthJA . . . . . . . . . . . . . . . . . . . . . . . . 65K/W Note 1. Equivalent to discharging a 200pF capacitor through a 0 series resistor.
Electrical Characteristics: (VP = 12V, TA = +25C unless otherwise specified)
Parameter Supply Positive Supply Voltage (Pin1) Supply Current Internal Reference Voltage Internal Reference Voltage Temperature Coefficient Power Supply Ripple Rejection Supply Voltage (Pin1) to Ensure All Internal Reference Voltages Composite Sync Input (AC-Coupled, V10 = 5V) Sync Amplitude of Video Input Signal (Pin9) Top Sync Clamping Level Slicing Level Above Top Sync Level Allowed Source Resistance for 7% Duty Cycle Differential Input Resistance Charging Current of Coupling Capacitor Vertical Sync Integration Time to Generate Sync Pulse RS r9 I9 tint Sync on Green, RS = 50 Vi sync > 200mV During Sync V9 > 1.5V fH = 31kHz, I18 = -1.050mA fH = 64kHz, I18 = -2.169mA fH = 100kHz, I18 = -3.388mA Horizontal Sync Input (DC-Coupled, TTL-Compatible) Sync Input Signal (Peak Value, Pin9) Slicing Level Minimum Pulse Width Rise Time and Fall Time Input Current tp tr, tf I9 V9 = 0.8V V9 5.5V Automatic Horizontal Polarity Switch (H-Sync on Pin9) Horizontal Sync Pulse Width Related to tH (Duty Cycle for Automatic Polarity Correction) Delay Time for Changing Sync Polarity Sync Input Signal (Peak Value, Pin10) Slicing Level Input Current Maximum Vertical Sync Pulse Width for Automatic Vertical Polarity Switch Horizontal Mode Detector Output (VGA Mode) Output Saturation Voltage LOW (For Modes 1, 2, and 3) Output Voltage HIGH Load Current to Force VGA Mode-Dependent Vertical and Parabola Amplitudes Output Current I7 V7 I7 = 6mA Mode 4 Modes 1, 2, and 3 Mode 4 - - 2 - 0.275 0.33 - - 0 VP 6 - V V mA mA I10 tp V 0 < V10 < 5.5V tp H/tH tp Vi sync - 0.3 1.7 1.2 - - - - - 1.4 - - 30 1.8 - 1.6 10 300 % ms V V A s Vu sync 1.7 1.2 700 10 - - - 1.4 - - - - - 1.6 - 500 -200 10 V V ns ns A A Vi sync Sync on Green - 1.1 90 - - 1.3 7 3.5 2.5 300 1.28 120 - 80 2.0 10 5.0 3.4 - 1.5 150 1.5 - 3.0 13 6.5 4.5 mV V mV k A s s s Vref TC PSRR VP TA = +20 to +100C f = 1kHz Sine Wave f = 1MHz Sine Wave 6.0 - 60 25 9.2 6.25 - 75 35 - 6.5 90 - - 16.0 V 10-6/K dB dB V VP IP I18 = -1.05mA I18 = -3.388mA 9.2 - - 12.0 36 40 16.0 44 49 V mA mA Symbol Test Conditions Min Typ Max Unit
Vertical Sync Input (DC-Coupled, TTL-Compatible,,V-Sync on Pin10)
Electrical Characteristics (Cont'd): (VP = 12V, TA = +25C unless otherwise specified)
Parameter VGA/Autosync Mode Switch Input Voltage LOW to Force Autosync Mode Horizontal Comparator PLL1 Upper Control Voltage Limitation Lower Control Voltage Limitation Control Current Horizontal Oscillator Center Frequency Deviation of Center Frequency Temperature Coefficient Relative Holding/Catching Range External Oscillator Current Voltage at Reference Current Input (Pin18) Horizontal PLL2 Upper Clamping Level of Flyback Input Lower Clamping Level of Flyback Input H-Flyback Slicing Level Delay Between Middle of Sync and Middle of H-Flyback Related to tH Upper Control Voltage Limitation Lower Control Voltage Limitation Control Current PLL2 Control range Related to tH Horizontal Output (Open-Collector) Output Voltage LOW tH Duty Cycle Threshold to Activate Too Low Supply Voltage Protection Threshold to Activate Too Low Supply Voltage Protection Jitter of Horizontal Output tH V3 tp/tH VP Horizontal Output OFF Horizontal Output ON f = 31kHz f = 64kHz f = 100kHz Horizontal Clamping/Blanking Generator Output Output Voltage LOW Blanking Output Voltage Clamping Output Voltage Internal Sink Current for All Output Levels Clamping Pulse Start Clamping Pulse Width Steepness of Rise and Fall Times I8 t8 tclp S V8 Internal V Blanking H-Sync on Pin9 H and V Scanning External Load Current - 1.6 5.15 2.3 - 0.8 - - 1.9 5.4 2.9 - 1.0 60 0.9 2.2 5.65 3.5 -3.0 1.2 75 V V V mA mA s ns/V I3 = 20mA I3 = 60mA - - 42 - - - - - - - 45 5.6 5.8 - - - 0.3 0.8 48 - - 3.5 1.9 1.2 V V % V V ns ns ns I20 t/tH td/tH V20 V2 I2 = 6mA I2 = -1mA - - - - - - - 30 5.5 -0.75 3.0 3.0 6.2 4.8 0.083I18 - - - - - - - - - V V V % V V A % fOSC fOSC TC H/tH I18 V18 R18 = 2.4k (Pin18), C19 = 10nF (Pin19) - - - 6.0 -0.5 2.35 31.45 - +200 6.5 - 2.5 - 3.0 7.3 -4.3 2.65 kHz % % mA V V17 I17 - - - 5.9 5.1 0.083I18 - - - V V A V7 0 - 50 mV Symbol Test Conditions Min Typ Max Unit
+300 10-6/K
With End of H-Sync
Electrical Characteristics (Cont'd): (VP = 12V, TA = +25C unless otherwise specified)
Parameter Vertical Oscillator (Vref = 6.25V) Vertical Free-Running Frequency Nominal Vertical Sync Range Voltage on Pin15 Delay Between Sync Pulse and Start of Vertical Scan in VGA/XGA Mode Delay Between Sync Pulse and Start of Vertical Scan in Autosync Mode Control Current for Amplitude Control Capacitor for Amplitude Control Vertical Differential Output Differential Output Current Between Pin5 and Pin6 (Peak-to-Peak Value) Maximum Offset Current Error Maximum Linearity Error Vertical Amplitude Adjustment (In Percent of Output Signal) Input Voltage Adjustment Current VGA Mode-Dependent Pre-Settings Activated by an External Resistor on Pin7 Mode 1 Mode 2 Mode 3 Mode 4 Autosync Operation (VGA Operation Disabled) E/W Output (Note 2) Bottom Output Signal During Mid-Scan (Pin11) Top Output Signal During Flyback Temperature Coefficient of Output Signal E/W Amplitude Adjustment (Parabola) Input Voltage (Pin14) Adjustment Current V14 I14 100% Parabola Typicall 28% Parabola - -110 - 5.0 -120 0 - -135 - V A A TC V11 Internally Stabilized 1.05 4.2 - 1.2 4.5 - 1.35 4.8 250 V V 10-6/K Table 2, Note 2, V7 < 50mV V13 I13 Io/t Table 2,Note 2 116.1 116.8 117.4 101.6 102.2 102.8 - - - 100 100 100 - - - % % % % % Iomax (100%) Iomin (Typically 58%) - -110 - 5.0 -120 0 - -135 - V A A Io Mode 3, I13 > -135A, R15 = 22k Io = 1mA 0.9 - - 1.0 - - 1.1 2.5 1.5 mA % % I12 C12 fo fV V15 td R15 = 22k, C16 = 0.1F No fo Adjustment R15 = 22k Measured on Pin8, Activated by an External Resistor on Pin7 Measured on Pin8, V7 < 50mV - 50 2.8 500 42 - 3.0 575 - 110 3.2 650 Hz Hz V s s A F Symbol Test Conditions Min Typ Max Unit
240 - -
300 200 -
360 - 0.18
Note 2. Io/t relative to value of Mode 3. Note 3. Parabola amplitude tracks with mode-dependent vertical amplitude but not with vertical amplitude adjustment. Tracking can be achieved by a resistor from vertical amplitude potentiometer to Pin14.
Functional Description: Horizontal Sync Separator and Polarity Correction An AC-coupled video signal or a DC-coupled TTL sync signal (H only or composite sync) is input on Pin9. Video signals are clamped with top sync on 12.8V, and are sliced at 1.4V. This results in a fixed absolute slicing level of 120mV relative to top sync. DC-coupled TTL sync signals are also sliced at 1.4V, however with the clamping circuit in current limitation. The polarity of the separated sync is detected by internal integration of the signal, then the polarity is corrected. The polarity information is fed to the VGA mode detector. The corrected sync is the input signal for the vertical sync integrator and the PLL1 stage. Vertical Sync Separaztor, Polarity Correction and Vertical Sync Integrator DC-coupled vertical TTL sync signals may be applied to Pin10. They are sliced at 1.4V. The polarity of the separated sync is detected by internal integration, then polarity is corrected. The polarity information is fed to the VGA mode detector. If Pin10 is not used, it must be connected to GND. The separated Vi sync signal from Pin10, or the integrated composite sync signal from Pin9 (TTL or video) directly triggers the vertical oscillator. VGA Mode Detector and Mode Output The three standard VGA modes and a 4th not fixed mode are decoded by the polarities of the horizontal and the vertical sync input signals. An external resistor (from VP to Pin7) is necessary to match this function. In all three VGA modes the correxct amplitudes are activated. The presence of the 4th mode is indicated by HIGH on Pin7. This signal can be used externally to switch any horizontal or vertical parameters. VGA Mode Detector Input For autosync operation the voltage on Pin7 must be externally forced to a level of < 50mV. Vertical amplitude pre-settings for VGA are then inhibited. The delay time between vertical trigger pulse and the start of vertical deflection changes from 575 to 300s (575s is needed for VGA). The vertical amplitude then remains constant in a frequency range from 50 to 110Hz. Clamping and V-Blanking Generator A combined clamping and V-blanking pulse is available on Pin8. The lower level of 1.9V is the blanking signal derived from the vertical blanking pulse from the internal vertical oscillator. Vertical blanking equals the delay between vertical sync and the start of vertical scan. By this, an optimum blanking is acheived for VGA/XGA as well as for multi-frequency operation (selectable via Pin7). The upper level of 5.4V is the horizontal clamping pulse with internally fixed pulse width of 0.8s. A mono flop, which is triggered by the trailing edge of the horizontal sync pulse, generates this pulse. If composite sync is applied one clamping pulse per H-period is generated during V-sync. The pahse of the clamping pulse may change during V-sync. PLL1 Phase Detector The phase detector is a standard one using switched current sources. The middle of the sync is compared with a fixed point of the oscillator sawtooth voltage. The PLL filter is connected to Pin17. If composite sync is applied, the distributed control voltage is corrected during V-sync. Horizontal Oscillator This oscillator is a relaxation type and requires a fixed capacitor of 10nF at Pin19. By changing the current into Pin18 the whole frequency range from 13 to 100kHz can be covered. The current can be generated either by a frequency to voltage converter or by a resistor. A frequency adjustment may also be added if necessary. The PLL1 control voltage at Pin17 moduloates via a buffer stage the oscillator thresholds. A high DC- loop gaqin ensures a stable phase relationship between horizontal sunc and line flyback pulses.
Functional Description (Cont'd): PLL2 Phase Detector This pahse detector is similar to the PLL1 phase detector. Line flyback signals (Pin2) are compared with a fixed point of the oscillator sawtooth voltage. Delays in the horizontal deflection circuit are compensated by adjusting the phase relationship between horizontal sync and horizontal output pulses. A certain amount of phase adjustment is possible by injecting a DC current froma an external source into the PLL2 filter capacitor on Pin20. Horizontal Driver This open-collector output stage (Pin3) can directly drive an external driver transistor. The saturation voltage is 300mV at 20mA. To protect the line deflection transistor, the horizontal output stage does not conduct at VP < 6.4V (Pin1). Vertical Oscillator and Amplitude Control This stage is designed for fast stabilization of the vertical amplitude after changes in sync conditions. The free-running frequency fo is determined by the values of RVOS and CVOS. The recommended values should be altered marginally only to preserve the excellent linearity and noise performance. The vertical drive currents I5 and I6 are in relation to the value of RVOS. Therefore, the oscillator frequency must be determined only by CVOS on Pin16. fo = 1 10.8 x RVOS x CVOS
To acheive a stabilized amplitude the free-running frequency fo (without adjustment) must be lower than the lowest occurring sync frequency. The contributions shown in Table 1 can be assumed. Table 1. Calculation of fo Total Spread Contributing Elements Minimum Frequency Offset Between fo and the Lowest Trigger Frequency Spread of IC Spread of R (22k) Spread of C (0.1F) Total Results for 50 to 110Hz application: fo = 50Hz = 42Hz 1.19 % 10 3 1 5 19
Table 2. VGA Modes
Mode Horizontal/Vertical Sync Polarity +/- -/+ -/- +/+ */* Horizontal Frequency (kHz) 31.45 31.45 31.45 Fixed by External Circuitry Fixed by External Circuitry Vertical Frequency (Hz) 70 70 60 - - Number of Active Lines 350 400 480 - - Output Mode Pin7 LOW LOW LOW HIGH Forced to GND
1 2 3 4 Autosync
Pin Connection Diagram
VP 1 Horiz Flyback Input 2 Horiz Output 3 GND (0V) 4 Vert Output 1/Neg-Going Sawtooth 5 Vert Output 2/Pos-Going Sawtooth 6 4th Mode Output/Autosync In 7 Clamping/Blanking Pulse Out 8 Horiz Sync/Video In 9 Vert Sync In 10
20 19 18 17 16 15 14 13 12 11
PLL2 Phase Horiz OSC Capacitor Horiz OSC Resistor PLL1 Phase Vert OSC Capacitor Vert OSC Resistor E/W Amp Adj Input (Parabola) Vert Amp Adj Input Cap for Amp Control E/W Output (Parabola to Driver Stage)
20 1
11 .280 (7.12) Max 10
.995 (25.3) Max
.300 (7.62)
.280 (7.1)
.100 (2.54)
.125 (3.17) Min
.385 (9.8)

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